As the size of integrated circuits is reduced and the number of integrated circuits on a chip increases, the components that make up the circuits must be positioned closer together in order to comply with the limited space available on a typical chip. Current research, therefore, is directed towards achieving a greater density of active components per unit area of a semiconductor substrate. Accordingly, effective isolation between circuits is becoming more important for ensuring optimum semiconductor performance. Conventional isolation of circuit components in modern integrated circuit technology takes the form of shallow trenches, which are etched into the semiconductor substrate and filled with an insulating material, such as silicon dioxide. These areas are generally referred to in the art as shallow trench isolation (STI) regions. STI regions serve to isolate the active regions of the integrated circuit.
A problem associated with STI processing is planarization of the semiconductor substrate following trench formation (i.e., after the trench is etched and then filled with an insulation material). In particular, after trenches are filled with insulation material, it is necessary to selectively remove protrusions of the insulation material from the “mesa” regions between each trench of the semiconductor substrate. This requires the selective removal of the oxide insulating material over the barrier film (typically a nitride material) that tops the mesa regions. The complete removal of oxides from the mesa regions must be accomplished with minimal thinning of the underlying barrier film, in order to ensure uniform thickness of the barrier film across the semiconductor substrate. Planarity of the semiconductor substrate is, in fact, crucial for maximal semiconductor performance. A highly planar surface topography reduces the potential for current leakage (i.e., short-circuiting) between active regions of the integrated circuit. In addition, a high degree of planarity reduces the potential for depth of focus lithography problems during subsequent interconnect processing steps. Accordingly, excellent planarization or polishing processes following trench formation are critical for ensuring optimum semiconductor performance.
Attempts to solve the problem of providing a highly planarized integrated circuit structure, after having formed oxide-filled STI regions in the substrate, have resulted in a number of planarization schemes. Conventional planarization schemes include, for example, ‘integration schemes’ which combine conventional chemical-mechanical polishing (CMP) slurries with dummy structures, oxide reverse masks and etches, dual nitrides, hard masks, and/or resist blocks. U.S. Pat. No. 5,721,173 (Yano et al.), for example, is directed to a method of forming a trench isolation structure involving a two-step process of planarizing by CMP using a slurry and, then, wet-etching with an HF solution. Most conventional schemes, however, are time-consuming and expensive, and can be inefficient during one or more processing steps.
A need remains, therefore, for polishing systems, compositions, and/or methods that, when used alone or in combination with conventional planarization or integration schemes, will exhibit minimal barrier film thinning and will result in maximal barrier film planarity (i.e., thickness uniformity) across a composite substrate, particularly after the substrate has undergone shallow trench isolation processing. The present invention seeks to provide such a polishing system, composition, and method. These and other advantages of the present invention will be apparent from the description of the invention provided herein.